1. Field of the Invention
The present invention relates to semiconductor devices and their manufacture, and more specifically to semiconductor devices having metal vias and their manufacture.
2. Description of the Related Art
A typical semiconductor chip includes active devices such as transistors and wiring referred to as conductive interconnects that connect the transistors together in form of an integrated circuit to perform the function of the chip. In general, with each generation of semiconductor chips, the sizes of transistors and conductive interconnect becomes smaller, mostly to provide a greater number of transistors (and function) for the size of the chip being made.
Semiconductor chips typically have an active semiconductor device area which is adjacent to a top or major surface of the chip. The active area typically is disposed in horizontal directions which run parallel with the top surface. The conductive interconnects include wiring lines that run in the horizontal directions of the top surface above the transistors. The conductive interconnects also include vias which are vertical electrically conductive elements which can connect wiring lines that run horizontally at one level of the chip with other wiring lines that run horizontally at a different level of the chip. A special type of via known as a “contact via” vertically connects elements such as transistors at one level of the chip with other elements such as wiring lines above that level. In CMOS (complementary metal oxide semiconductor) chips, a contact via typically connects to a source, drain or gate of a transistor. Contact vias are very narrow structures which need not be any wider than the smallest photolithographic feature size or “groundrule” to which elements of the chip having the smallest width can be patterned. For example, a contact via can have a width as small as a width of a gate conductor of a transistor of the chip. Contact vias can also have large height in relation to their width. Contact vias are often considered to be “high aspect ratio” elements because the height of a contact via can be more than 1.5 times as great as the width. High aspect ratio openings typically require a greater degree of process control when filling them with a metal than openings which do not have high aspect ratio.
In advanced semiconductor chips, wiring typically consists essentially of copper. Copper performs well electrically because of its high electrical conductivity, among the highest of the elemental metals. However, special processing is required to enable copper to be used in conductive interconnects. Copper can diffuse into silicon and some dielectric materials such as silicon dioxide and can alter the properties of those materials. To avoid such outcome, copper interconnects can be formed in lined openings in a dielectric layer and with special capping layers to prevent copper ions from migrating into the dielectric layer. Copper generally is not used in contact vias. It can be difficult to adequately control a process to form the required liners and a capping layer to encase the copper within openings.
Typically, even when the wiring lines on a chip include copper, contact vias are formed by depositing a refractory metal such as tungsten into contact openings by processes such as chemical vapor deposition (“CVD”) or physical vapor deposition (“PVD”). Tungsten has been used for this purpose for many years, even though its resistivity as a bulk material (at 5.6 micro-ohm-cm) is greater than copper's (at 1.7 micro-ohm-cm). Tungsten fills high aspect ratio openings well and tungsten does not migrate as much into dielectric materials as copper. However, the increasingly small size of contact vias make tungsten less desirable than before.
Referring to FIG. 1A, a hole 12 is formed in a dielectric layer of a wafer 20. The hole typically partially exposes an underlying feature such as a silicide or doped semiconductor region 8 of a device aligned with a bottom surface 14 of the hole 12. An adhesion layer and a barrier layer (neither shown in FIG. 1A) may be formed initially at the bottom surface 14 and along a wall 16 of the hole. A CVD process deposits a layer of tungsten 10 conformally over the bottom surface 14 and over the wall 16 of a hole 12 in the dielectric layer. The process also deposits tungsten over an exposed major surface 18 of the wafer 20. As seen in FIG. 1B, as deposition progresses, the thickness 22 of the deposited tungsten layer increases uniformly on the wall 16. Eventually, when filling the hole, the deposited tungsten 10 forms a seam 24 (FIG. 1C) extending in vertical directions 26, i.e., in a direction of the height of the hole from the bottom surface 14. At the seam, the deposited tungsten may not completely fill the hole. Instead, a void may exist which is occupied by air or other material. The volume occupied by the seam 24 and any voids can make the contact via less electrically conductive than if the contact via were completely filled with a metal.